1. Field of the Invention
The present invention is directed to a circuit and method for the multiple use of a digital transversal filter wherein, in a coefficient block having n coefficients, two multiplier units are provided which are subject to multiple use if an internal clock of the filter is faster, by an integral order of magnitude, than an external clock which is required by the filter.
2. Description of the Prior Art
Bit plane and modified bit plane architectures are often used for the highly efficient implementation of digital transversal filters. If the necessary external data rate (sampling rate) at which a filter function is to be carried out is significantly below the internal data rate with which filter switching operations can be implemented using modern switching technologies, a reduction in the chip area for a given throughput rate of the transversal filter can be achieved through the multiple use of the transversal filter.
During multiple use of the transversal filter, a plurality of arithmetic substeps are successively carried out at a plurality of internal clock pulses during one external clock pulse in an arithmetic unit. In such a case, it is necessary to ensure, in particular, that the additional expenditure on the sequential feeding of the operands for the arithmetic substeps as well as the storage of intermediate results is not too large.
Bases for the implementation of digital transversal filters in bit plane and modified bit plane architectures are known and described in T. Noll, Carry-Save Architectures for High-Speed Digital Signal Processing, Journal of the VLSI Signal Processing, Vol. 3, Kluwer Academic Publishers, Boston, pp. 121-140, 1991).
In circuit arrangements in which the necessary external data rate at which a transversal filter function is to be carried out is higher than the internal data rate with which transversal filter switching operations can be implemented, it is possible to use linearly scaling parallelization concepts which are known (U. Seuben et al, Digitale Filter fur Videosignale, Design und Elektronik [digital filters for video signals, design and electronics], No. 9, page 69, 1991).
The connecting together of a plurality of component filters to form one complex-valued filter is described, for example, in S. Quereshi, Adaptive Equalization, Proc. of the IEEE, Vol. 73, No. 9, pp. 1349 to 1387, 1985). M. Vaopel and H. Meyr, High Speed FIR Filter Architectures with Scalable Rates, Internat. Symposium on Circuits and System (ISCAS) VLSI, London, May 40-June 2, Vol. 4, May 30, 1994 discloses principles of high-speed FIR filter architectures (FIR=Finite Impulse Response).